Nava

Post-Training Optimization Engineer (LLM Inference & Efficiency)

Nava

Bengaluru•On-site•1-3 Yrs•1 day ago

AIMachine LearningOptimization

Optimize LLM inference pipelines for efficiency across hardware.

Optimize LLM inference pipelines for latency, throughput, and memory efficiency across GPU/TPU hardware—using quantization, pruning, kernel fusion, and runtime scheduling.
Implement and benchmark model compression techniques (INT4/INT8/FP8, LoRA, Sparse attention) to reduce model size while preserving performance.
Integrate and tune LLM serving frameworks (vLLM, TensorRT-LLM, HuggingFace TGI, ONNX Runtime) for high-throughput, low-latency inference in cloud and on-premise environments.
Collaborate with ML researchers and infrastructure engineers to profile bottlenecks and implement hardware-aware optimizations using CUDA, Triton, or custom kernels.
Design and automate model benchmarking suites to track performance regression, memory footprint, and cost-per-token across model versions and hardware targets.
Document optimization playbooks and contribute to internal tooling for repeatable, scalable model deployment workflows.
PyTorch
TensorRT
vLLM
Quantization (INT4/INT8/FP8)
CUDA
ONNX Runtime
Triton Inference Server
LLM Inference Optimization

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